1. Field of the Invention
This invention relates generally to methods and structures for improving byte-oriented encoding, and more particularly to methods and structures that provide improvements in high speed encoding.
2. Description of the Related Art
It is well known that 8B/10B encoders employ a partitioned design. That is, such encoders are designed to consolidate a 5B/6B code and 3B/4B code into a compound 8B/10B code, using separate coders for each operation. See, for example, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code” by A. X. Widmer and P. A. Franaszek, which describes a typical 8B/10B encoder and provides a discussion on eight-bit to ten-bit encoding logic. This paper is incorporated herein by reference. In such a partitioned encoder, both the positive and the negative edges of the clock are used to encode data. In conventional design, at the positive edges data is encoded from 5B to 6B, and at the negative edges data is encoded from 3B to 4B. However, using both edges of the clock has some disadvantages, as well as technical difficulties.
One disadvantage is that more I/O pins are needed for the circuit chip embodying the encoder as a result of using both clock edges to encode data. Moreover, with this prior art design, a 50% clock duty cycle is needed to complete the encoding of 5B to 6B and 3B to 4B. As a result of this clocking scheme, it is also sometimes difficult to maintain the run length of an encoded binary signal string to five or less. A long run-length, e.g., greater than five destabilizes clock data recovery logic and produces unreliable clock data recovery in a high-speed data communication application, such as a peripheral component interconnect express card. Consequently, such conventional encoders are not well suited for high-speed, i.e., greater than 250 MHz, encoding applications.